Monte Carlo simulations of high-performance implant free In_0.3Ga_0.7 nano-MOSFETs for low-power CMOS applications

No abstract available

180nm metal gate, high-k dielectric, implant-free III--V MOSFETs with transconductance of over 425 μS/μm

Abstract: Data is reported from 180 nm gate length GaAs n-MOSFETs with drive current (Ids,sat) of 386 μA/μm (Vg=Vd =1.5 V), extrinsic transconductance (gm) of 426 μS/μm, gate leakage ( jg,limit) of 44 nA/cm2, and on resistance (Ron) of 1640 Ω μm. The gm and Ron metrics are the best values reported to date for III-V MOSFETs, and indicate their potential for scaling to deca-nanometre dimensions

Sub-micron, Metal Gate, High-к Dielectric, Implant-free, Enhancement-mode III-V MOSFETs

The performance of 300nm, 500nm and 1μm metal gate, implant free, enhancement mode III-V MOSFETs are reported. Devices are realised using a 10nm MBE grown Ga2O3/(GaxGd1-x)2O3 high-κ (κ=20) dielectric stack grown upon a δ-doped AlGaAs/InGaAs/AlGaAs/GaAs heterostructure. Enhancement mode operation is maintained across the three reported gate lengths with a reduction in threshold voltage from 0.26 V to 0.08 V as the gate dimension is reduced from 1 μm to 300 nm. An increase in transconductance is also observed with reduced gate dimension. Maximum drain current of 420 μA/μm and extrinsic transconductance of 400 µS/µm are obtained from these devices. Gate leakage current of less than 100pA and subthreshold slope of 90 mV/decade were obtained for all gate lengths. These are believed to be the highest performance submicron enhancement mode III-V MOSFETs reported to date

Enhancement Mode n-MOSFET with High-κ Dielectric on GaAs Substrate

In this paper, we report MOS heterostructures grown by molecular beam epitaxy on III-V substrates, employing a high-κ dielectric stack comprised of gallium oxide and gadolinium gallium oxide. Mobilities exceeding 12,000 and 6,000 cm2/Vs, for sheet carrier concentration ns of about 2.5x1012 cm-2 were measured on MOSFET structures on InP and GaAs substrates, respectively. These structures were designed for enhancement mode operation and include a 10 nm thick strained InGa1-xAs channel layer with In mole fraction x of 0.3 and 0.75 on GaAs and InP substrates, respectively

1 μm gate length, In_0.75Ga_0.25As channel, thin body n-MOSFET on InP substrate with transconductance of 737μS/μm

The first demonstration of implant-free, flatband-mode In<sub>0.75</sub>Ga<sub>0.25</sub>As channel n-MOSFETs is reported. These 1 μm gate length MOSFETs, fabricated on a structure with average mobility of 7720 cm<sup>2</sup>/Vs and sheet carrier concentration of 3.3×10<sup>12</sup> cm<sup>-22</sup>, utilise a Pt gate, a high-k dielectric (k≈20), and a δ-doped InAlAs/InGaAs/InAlAs heterostructure. The devices have a typical maximum drive current (I<sub>d,sat</sub>) of 933 μA/μm, extrinsic transconductance (g<sub>m</sub>) of 737 μS/μm, gate leakage (I<sub>g</sub>) of 40 pA, and on-resistance (R<sub>on</sub>) of 555 Ωμm. The g<sub>m</sub> and R<sub>on</sub> figures of merit are the best reported to date for any III-V MOSFET

High Mobility III-V MOSFETs For RF and Digital Applications

Developments over the last 15 years in the areas of materials and devices have finally delivered competitive III-V MOSFETs with high mobility channels. This paper briefly reviews the above developments, discusses properties of the GdGaO/Ga2O3 MOS systems, presents GaAs MOSFET DC and RF data, and concludes with an outlook for high indium content channel MOSFETs. GaAs based MOSFETs are potentially suitable for RF power amplification, switching, and front-end integration in mobile and wireless applications while MOSFETs with high indium content channels are of interest for future CMOS applications

A low damage etching process of sub-100 nm platinum gate line for III-V metal-oxide-semiconductor field-effect transistor fabrication and the optical emission spectrometry of the inductively coupled plasma of SF6/C4F8

This paper presents a low damage inductively coupled plasma (ICP) etching process to define sub-100 nm platinum gate lines for III–V metal–oxide–semiconductor field-effect transistors (MOSFETs) fabrication. In this process, a negative resist etching mask patterned by electron beam lithography is used to define the high resolution platinum features using a combination of SF<sub>6</sub> and C<sub>4</sub>F<sub>8</sub> etch gases. Systematic investigation of the impact of various etch conditions, such as coil and platen power, gas composition, chamber pressure on etch rate and profile, resulted in a controllable etching process. Optical emission spectra of the ICP plasma have been checked for better understanding the etching mechanism. Etch induced damage of the underlying device channel of the III–V MOSFET materials has been evaluated through monitoring the sheet resistance variation of the materials at room temperature, which showed the process does not significantly degrade the electrical properties of the underlying device channel under optimized conditions

A Low Damage Subtractive Ohmic Contact Process for III-V Mosfets

No abstract available

EFTEM and EELS SI: tools for investigating the effects of etching processes for III-V MOSFET devices

High quality oxides layers are now available for MOSFETs on GaAs. For successful devices, suitable process schemes are required. In this paper we show an investigation of an etching process on a GaAs/Ga2O3/GGO dielectric gate stack. This investigation has been carried out using EFTEM and EELS SI. EFTEM provides a quick analysis on the structure while EELS SI offers much better resolution and the possibility to quantitatively characterize the material